ASML's High-NA EUV rollout — the four shipped systems.

The four systems and where they sit — a precise inventory

TSMC's High-NA installation in Hsinchu sits inside the Research and Development centre that anchors the foundry's process technology development, with the EXE:5200 designated specifically for N2P, A14, and the sub-A14 nodes that are in active research. The system has been characterised by TSMC's technology development organisation, in the November 2025 quarterly briefing, as having moved from initial qualification to active wafer processing during Q1 2026, with the system contributing to the most demanding metal layers on the N2P production wafers that began shipping from Fab 20 in March. The contribution at this stage is bounded: the High-NA system at the R&D centre runs an estimated 1,200 wafers per month on production-relevant patterning, with the remaining capacity dedicated to the A14 process development effort that targets risk production in 2027. The system's commercial role expands when Fab 20 phase two and Fab 21 in Arizona receive their own High-NA deliveries through 2026 and 2027.

Intel's High-NA installation at the D1X facility in Hillsboro, Oregon, has been the most publicly disclosed of the four. The company's Foundry leadership ran a press demonstration in late 2024 with the system positioned as the anchor capability for the 14A process node — Intel's competitive response to TSMC's A14. The 14A timeline, as articulated by the Intel Foundry organisation, targets risk production in 2027 with first customer wafers in 2028, contingent on the High-NA system clearing its qualification milestones on the targeted device geometry. The Intel installation has been processing test wafers since the second quarter of 2025, and the company's published commentary in the Q1 2026 earnings cycle characterised the system as on track for the 14A development timeline. The internal record is more contested. Sources familiar with the Intel Foundry organisation describe the High-NA qualification at D1X as running approximately one quarter behind the original development schedule, with the slippage attributed to the same stochastic-defect issues that the broader High-NA ecosystem has been working through.

Samsung Foundry's High-NA installation at the Hwaseong S5 fab is the most strategically loaded of the four. Samsung's competitive position relative to TSMC on the leading-edge envelope has been defined by the SF3 and SF2 node yield curves, both of which have underperformed against the corresponding TSMC nodes through the development cycle. The High-NA system at Hwaseong is positioned as the anchor capability for SF1.4 — Samsung's response to TSMC's A14 — with risk production targeted for late 2027 and first customer wafers in 2028. The customer base at SF1.4 is, in the published Samsung commentary, framed against hyperscaler custom silicon programmes and a renewed effort to win Qualcomm and NVIDIA design-ins that the company lost on prior generations. The High-NA installation is the technical credential against which those design-in conversations are being conducted. The Samsung Foundry president, Si-young Choi, characterised the High-NA installation in the company's January 2026 management committee briefing as the most consequential capital expenditure decision the foundry has made in five years.

Imec's High-NA installation at Leuven is the only one of the four that sits in a non-customer research environment, and it serves a function distinct from the three foundry deployments. Imec runs collaborative process development for the broader EUV ecosystem under separate framework agreements with ASML, TSMC, Intel, Samsung, the major equipment vendors, and the leading resist chemistry suppliers. The Leuven installation is the platform on which the next-generation resist chemistry — the JSR and Tokyo Ohka stack scheduled for production qualification in late 2026 — is being co-developed alongside the foundry-side process integration. The system also anchors the European Commission's research-side response to the foundry gap, providing the EU industrial AI ecosystem with access to leading-edge process development that it cannot, on the current capex commitments, deliver through domestic fab construction. The 6 May 2026 acceptance at Imec was the milestone that completed the first-wave shipment commitment. The second wave begins later in 2026.

The second-wave deliveries through Q3 and Q4 2026 are scheduled across the same customer set with the addition of TSMC Fab 20 phase two — a second TSMC system specifically committed against the volume production environment rather than the R&D centre — and a second Intel system for the D1X follow-on facility. ASML's published delivery cadence is approximately five systems per year through 2026 and 2027, ramping to eight systems per year by 2028 as the Veldhoven assembly capacity expands. The cadence is the binding constraint on the leading-edge ramp at every foundry: the second-wave systems are committed at full price with multi-year deposit structures, and the foundry that does not commit its next system on the published delivery slot loses that delivery to the next customer in the queue. The competitive dynamics on system access are tighter than the public commentary suggests.

The technical issues — stochastic defects, throughput, and the resist problem

The High-NA system's manufacturing envelope at the foundry-side has, in the first 18 months of operational data, settled at a position more constrained than ASML's commercial launch positioning suggested. The headline technical issue is stochastic patterning defects: at single-exposure high-NA operating regimes, the resist response to the more aggressive optical pattern produces stochastic errors at a rate that the foundry-side mask and resist chemistry has not yet closed. The defect density at TSMC's R&D system in early 2026 was characterised, in technical commentary from the foundry's process development organisation, as approximately 3.2 times the defect density target that the production ramp will require. The path to closing that gap runs through three workstreams: the next-generation resist chemistry from JSR and Tokyo Ohka; the secondary mask blank improvements that AGC and Hoya are co-developing with the foundries; and the optical column calibration that ASML has continued to refine through the installed-base service programme.

The resist problem is the most binding of the three constraints. The current EUV resist chemistry — predominantly chemically amplified resists with metal-oxide cluster systems — was developed against the optical envelope of the prior-generation NXE:3800 platform and has been incrementally improved through the platform's commercial life. The High-NA optical envelope requires resist response characteristics that the current chemistry does not deliver at acceptable defect density. The JSR and Tokyo Ohka next-generation stack — internally referred to in foundry technical documents as the EUV-3 resist family — is in customer qualification at TSMC and Intel as of Q1 2026, with production readiness targeted for Q4 2026. The qualification has cleared the initial defect density milestones at lab scale but has not yet demonstrated full process integration at the volume production environment that the Fab 20 phase-two ramp will require. The lateness of the resist qualification relative to the foundry's broader 2nm production schedule is the principal reason that High-NA's contribution at Fab 20 phase one is bounded to the topmost metal layers.

Throughput is the second technical constraint, and it sits at a different point in the manufacturing envelope. The EXE:5200's published throughput specification is 220 wafers per hour at the 30 millijoule-per-square-centimetre dose target that the system was specified against. The achieved throughput at TSMC's R&D installation in Q1 2026 was approximately 170 wafers per hour, principally because the operating dose at the foundry-side process recipe has been raised to a higher figure — approximately 42 millijoules-per-square-centimetre — to reduce stochastic defect density. The dose-throughput trade-off is a standard EUV manufacturing tension that has been worked through across prior platform generations; the High-NA platform is at the early phase of the same curve. The path to higher throughput at acceptable defect density runs through the same resist chemistry improvements that bound the defect density today. The throughput envelope will lift through 2027 in step with the resist roadmap. It is not lifting in time for the H2 2026 ramp.

The mask blank problem is the third constraint and the most difficult to publicly characterise, because it depends on supplier-specific manufacturing capabilities that AGC and Hoya hold as competitive intellectual property. The High-NA system's optical envelope requires mask blanks with substantially tighter flatness and defect specifications than the prior-generation EUV platform, and the mask blank supply chain has been characterised by foundry process engineers as the most acute bottleneck in the broader High-NA ecosystem. AGC, the dominant supplier, has expanded its mask blank production capacity in Yokohama with a capex commitment that the company disclosed in its November 2025 mid-term plan, but the capacity expansion runs through late 2027. The mask blank supply through H2 2026 and H1 2027 is, on the published numbers, approximately 35 per cent below the demand profile that the four-system installed base requires for full duty-cycle operation. Foundries are managing the constraint through mask reuse strategies that limit the productive throughput of their installations.

The optical column calibration is the constraint that ASML directly owns and that the company has been most willing to discuss publicly. The High-NA optical system involves substantially tighter alignment specifications than the prior-generation platform, and the calibration drift behaviour through the first 12 months of operational data has been characterised as more acute than ASML's initial commercial expectations. The remediation has been through service-side adjustments that ASML's installed-base team has shipped across the four-system fleet, with the November 2025 calibration update characterised by the company as bringing the optical envelope into the specified operating range. The customer-side feedback on the calibration improvement has been broadly positive across the four sites, with the residual constraint sitting at the resist and mask blank workstreams that ASML does not directly control. The optical column will continue to mature through the installed-base programme. The principal remaining technical work sits outside ASML's direct manufacturing envelope.

The per-system price and the capex envelope — 380 million dollars on the line

ASML's published per-system price for the EXE:5200 is 380 million dollars at list, with delivery, installation, initial calibration, and the first-year service envelope pushing the total commitment to approximately 425 million dollars at the customer-side acceptance milestone. The five-year total cost of ownership — incorporating ongoing service, consumables, mask blank set, and the resist chemistry envelope — runs to approximately 510 million dollars per system. Those figures are at the foundry's procurement contract terms; second-tier customers without TSMC's purchasing leverage face higher figures across each line item. The capex envelope at the per-system level is what defines the structural limitation on the leading-edge customer base. The four systems shipped so far represent approximately 1.5 billion dollars in capex commitments at the foundry side, with the full five-year TCO commitment closer to 2 billion dollars. The numbers compound across the broader installed base as the second-wave deliveries land through 2026 and 2027.

The amortisation logic for the High-NA capex commitment differs from the prior-generation EUV platform because the productive throughput envelope is lower and the early-life service overhead is higher. ASML's installed-base service revenue across the EXE:5200 fleet in 2025 was approximately 320 million dollars — substantially higher per system than the equivalent NXE:3800 platform service envelope at the equivalent point in its commercial life. The service revenue carries higher gross margin than the system sales and is one of the principal reasons that ASML's profitability through 2026 has held against the broader semiconductor capex environment. The financial economics of the High-NA platform sit substantially in the installed-base service envelope, and that envelope expands as additional systems ship through 2027 and 2028. The cumulative service revenue across the EXE:5200 fleet through 2028, on the published delivery cadence, is approximately 1.4 billion dollars on a 14-system installed base.

The pricing posture on the second-wave deliveries has been the subject of competitive negotiations across the customer base. TSMC's purchasing leverage — through the volume commitment across the second-wave deliveries and the broader prior-generation installed base — has secured pricing terms on the EXE:5200 that other customers have not been able to match. Sources familiar with the TSMC contract structure describe the per-system price at TSMC as effectively 360 million dollars after volume rebates and service-bundling concessions, against the 380 million list price that smaller customers face. Intel's per-system price is closer to the list figure, reflecting the smaller volume commitment and the less mature installed-base relationship. Samsung's pricing sits between the two reference points. Imec's pricing is structured against the broader research consortium framework and is not directly comparable. The cumulative pricing differential across the second-wave deliveries is in the tens of millions of dollars per system — material on the per-system economics but small relative to the broader capex envelope.

The service-side economics are the strategic asset that ASML is most aggressively managing. The five-year service contract structure that the company has negotiated with each of the four current customers commits the customer to ongoing maintenance, calibration, and consumables procurement from ASML's service organisation through the installed life of the system. The contracts include performance commitments — uptime targets, calibration drift tolerances, defect density specifications — that ASML is responsible for delivering against. The commercial structure transfers ongoing risk to ASML in exchange for the recurring revenue commitment, and the company has been willing to accept the risk transfer because the recurring revenue per system is the largest line item in the customer relationship across the five-year window. The customers, on their side, gain predictable cost visibility against the high-stakes process integration that the High-NA platform enables.

The implications of the per-system economics for the broader competitive lithography environment are stark. The capex commitment to enter the leading-edge customer base — a single High-NA system at 425 million dollars all-in for first-year acceptance — exceeds the annual capex budget of every Chinese foundry except SMIC, and SMIC cannot procure the system under the export-control regime. The capex commitment also exceeds the annual capex budget of every European foundry except ESMC, and ESMC's near-term roadmap does not require High-NA. The customer base for the EXE:5200 across the next five years will be, by economic necessity, restricted to TSMC, Intel, Samsung, the research consortia that anchor the broader ecosystem, and at most one or two additional entrants among the hyperscaler custom-silicon programmes if any of those programmes commits to in-house manufacturing rather than continuing the foundry partnership model. The structural concentration of the High-NA installed base is the manufacturing-side counterpart to the structural concentration of the leading-edge accelerator market.

The export-control posture and Chinese counter-investment at SMIC

The export-control regime that governs ASML's High-NA exports to China has held through the eighteen months since the first system shipped. The Dutch government's regulation, coordinated with the US Department of Commerce's Entity List framework, prohibits the export of the EXE:5200 to mainland Chinese customers and extends the prior-generation NXE:3800 prohibition that has been in force since late 2023. The regulatory posture has been characterised in The Hague's published commentary as a technology-tier control rather than a country-specific embargo, with the practical effect that no Chinese foundry has access to the High-NA platform and that the leading-edge envelope in China is, on the import-side controls, capped at the prior-generation EUV platform — which is itself unavailable through the existing export licence regime since late 2023.

The Chinese counter-investment programme at SMIC has been more aggressive on the trailing-edge capacity envelope, where the export-control regime does not apply, than on the leading-edge envelope, where it does. SMIC's published capex for 2026 is approximately 8.7 billion dollars, distributed across capacity expansions at the existing Beijing, Shanghai, and Tianjin sites. The published 2026 wafer-start guidance is approximately 38,000 wpm of incremental 28nm-class capacity across the three sites, with smaller incremental commitments at the 14nm and 7nm-equivalent envelopes that the company has produced through the DUV-multipatterning workaround. The company's leading-edge work — the 7nm and 5nm-equivalent processes that the workaround enables — is constrained to approximately 15,000 wpm across the existing Shanghai fab, and the yield curve at those nodes is substantially below the TSMC equivalent at the same point in the process maturity cycle.

SMEE — Shanghai Micro Electronics Equipment, the leading Chinese lithography company — has continued the development programme that targets domestic substitution for the export-controlled ASML platforms. The published roadmap places first EUV demonstration in late 2027 with commercial readiness in 2029, and the 28-nanometre immersion prototype that the company demonstrated in late 2025 has entered customer qualification at SMIC. The technical envelope of the SMEE prototype is approximately two generations behind ASML's current commercial offerings — corresponding roughly to the ASML scanner technology of 2014 — and the production yield curve at the SMEE-equipped Chinese foundries has been characterised, in supplier commentary that has reached the broader analyst community, as substantially below the ASML-equipped foundry equivalents at the same node. The structural gap between SMEE's commercial trajectory and ASML's installed base has not narrowed materially through the eighteen months since the High-NA programme launched.

Huawei's silicon programme — anchored at SMIC's Shanghai fab — has produced two product launches that demonstrate the workaround's commercial viability without resolving the structural lag. The Kirin K9100 SoC, which shipped in the Mate 70 product family in late 2024, ran on the SMIC N7-equivalent process at approximately the production volume that the workaround supports. The follow-on Kirin K9200, which shipped in mid-2025, ran on a refinement of the same process at incrementally improved performance and yield. The company's published 2026 roadmap targets a Kirin K9300 on the SMIC N5-equivalent — pushed through the DUV-multipatterning workaround — for a Q4 2026 product launch. The volume profile across the three product generations is constrained by the workaround's economics: each generation runs at substantially lower yield than the TSMC equivalent, and the cost-per-good-die figure at SMIC's leading-edge production runs at approximately 2.3 times the TSMC equivalent at comparable nodes. The commercial economics of the Chinese leading-edge envelope are sustained through state subsidy more than through market pricing.

The political environment around the export-control regime has, through the May 2026 mid-term window, remained stable. The Trump administration's posture on China-tied semiconductor exports has been characterised by the administration's commerce secretary as continuity with the late-Biden administration framework, with the strategic priority placed on maintaining the technology-tier control rather than expanding the prohibition envelope. The Dutch government's posture has aligned with the US framework through coordinated diplomatic channels, and ASML's executive commentary has consistently characterised the company as compliant with the regime rather than advocating for either expansion or relaxation. The structural durability of the export-control regime has been the principal political variable, and it has held through eighteen months of administration transitions and parliamentary cycles in both jurisdictions. The next stress test arrives at the next US-China bilateral commerce summit, scheduled for September 2026 in Shanghai. The expected agenda includes a technology-tier control item but the published expectations from both sides are framed against continuity rather than reset.

Timeline implications for sub-2nm nodes — A14, 14A, SF1.4

The four-system installed base anchors the development of the three sub-2nm nodes that the leading-edge foundries have publicly committed against: TSMC A14, Intel 14A, and Samsung SF1.4. The published roadmaps target risk production for all three nodes in 2027 with volume production in 2028, and the structural dependency on the High-NA platform's manufacturing envelope is what synchronises the three foundries against a comparable timeline. The principal source of timeline divergence across the three nodes will be the resist chemistry maturity through 2026 and the broader process integration that each foundry brings to its installed base. TSMC's posture, by every available indicator, is the most advanced of the three. Intel's posture has improved through 2025 and 2026 against the difficult prior-decade history of the company's leading-edge struggles. Samsung's posture is the most contested, and the SF1.4 timeline relative to the published commitments will be the most consequential resolution of the next 18 months.

TSMC's A14 process node has been the subject of detailed technical disclosure at the IEDM 2024 and IEDM 2025 events, with the company committing to risk production in late 2027 and first customer wafers in 2028. The published density gain at A14 against N2P is approximately 15 per cent for logic and 12 per cent for SRAM, with performance-per-watt improvements of approximately 18 per cent at iso-frequency. The transistor architecture moves from the N2P nanosheet to a refined nanosheet with additional channel sheet stacking, and the EUV patterning shifts to a configuration in which the High-NA contribution extends across the broader critical-layer envelope rather than the constrained topmost-layer configuration at N2P. The published customer commitments at A14 include Apple — for the M6 family in late 2028 — and Nvidia, for the post-Rubin accelerator generation that the company has not yet formally named. The customer queue beyond Apple and Nvidia is, on the published commitments, qualitatively similar to the N2P customer set with the addition of the hyperscaler custom-silicon programmes that are upgrading from N3P or N2P baselines.

Intel's 14A process node carries the strategic burden of demonstrating that the company's Foundry organisation can deliver a leading-edge process at competitive yield and timeline against TSMC. The Pat Gelsinger transition, the subsequent restructuring, and the strategic reorientation toward the Foundry-as-customer business model have all reduced the political margin that the 14A development effort can operate against. The published timeline targets risk production in 2027 with first customer wafers in 2028, and the customer commitments include three publicly named anchor customers: Microsoft, for the Azure custom silicon programme; the US Department of Defense, under the Secure Enclave framework that the Trump administration has prioritised; and one additional commercial customer that Intel has not publicly named but that industry sources have characterised as a hyperscaler. The 14A success criteria are simultaneously technical, commercial, and political. The High-NA installation at D1X is the technical instrument against which the broader programme is measured.

Samsung's SF1.4 process node carries the most acute strategic stakes for the company's Foundry organisation, which has been losing market share to TSMC across the prior three node generations and has been unable to secure the design-in commitments from Nvidia and Qualcomm that the company built its leading-edge capex against. The published SF1.4 roadmap targets risk production in late 2027, but the equivalent published commitments at SF3 and SF2 missed their original timeline by approximately two quarters each. Sources familiar with the Samsung Foundry organisation describe the internal development posture at SF1.4 as more disciplined than the prior generations, with the High-NA installation at Hwaseong being managed by a process development team that has been restructured to address the yield curve underperformance that defined the SF3 and SF2 experience. The customer base at SF1.4, on the publicly known commitments, includes one hyperscaler custom-silicon programme and one commercial mobile customer. Neither of those commitments individually is sufficient to recover the foundry's competitive position relative to TSMC, and the strategic question is whether Samsung's investment in the SF1.4 envelope is the prelude to a more aggressive competitive push in the late-2020s timeframe or a managed retreat to a second-tier leading-edge position.

The structural implication of the High-NA installed base on the broader semiconductor industry is that the leading-edge fab roadmap is, for the rest of the decade, locked into the four-system framework and its incremental extensions. The customer set is fixed. The technical workstreams are public. The export-control regime is stable. The timeline for the sub-2nm nodes runs through 2027 and 2028 across the three competing foundries. The most consequential remaining variable is the resist chemistry maturity through Q4 2026 and the broader process integration that follows. ASML's role through that window is principally on the optical envelope and the installed-base service programme; the binding technical work sits at JSR, Tokyo Ohka, AGC, Hoya, and the foundry-side process integration organisations. The High-NA platform has been delivered to its customers. The leading-edge ramp now depends on the partners.

What to watch

The High-NA installed base will be tested across four workstreams through the second half of 2026 and the first half of 2027. The resolutions of those workstreams will set the timeline for the sub-2nm node generation and the competitive position of the four foundries that anchor the leading-edge envelope.

• Whether the JSR and Tokyo Ohka next-generation EUV-3 resist family clears production qualification at TSMC and Intel by the targeted Q4 2026 milestone; the resist roadmap is the binding constraint on the High-NA productive envelope, and any slippage extends the constrained topmost-metal-layer configuration at Fab 20 into a longer plateau than the foundry has guided.
• Whether AGC's mask blank capacity expansion in Yokohama lands on its published late-2027 schedule; the mask blank supply through H2 2026 and H1 2027 is approximately 35 per cent below the demand profile that the four-system installed base requires, and the foundry-side workarounds — principally mask reuse strategies — limit the productive throughput of the existing installations until the supply catches up.
• Whether the September 2026 US-China bilateral commerce summit produces any meaningful adjustment to the export-control regime; the political durability of the technology-tier control framework has been the principal constraint on Chinese foundry access to leading-edge tooling, and any softening of the regime would change the structural competitive environment that the four-system installed base operates against.
• Whether Intel's 14A development at D1X clears the High-NA qualification milestones on the originally committed timeline; the quarter of slippage that has been reported by sources familiar with the Intel Foundry organisation is recoverable if the broader resist and process integration workstreams land on schedule, but additional slippage compounds across the broader programme commitments and erodes the competitive position that the company has been working to rebuild.
• Whether Samsung Foundry's SF1.4 process development at Hwaseong demonstrates a meaningful yield curve recovery against the SF3 and SF2 baseline; the company's competitive position depends on delivering an SF1.4 node that is competitive with TSMC A14 on yield, performance, and customer commitments, and the High-NA installation at Hwaseong is the technical credential against which that competitive recovery is being measured.

Frequently asked

What does High-NA EUV actually do that the prior-generation EUV platform did not?

The High-NA EUV platform — the ASML EXE:5200 — operates with a numerical aperture of 0.55 against the prior-generation NXE:3800's 0.33. The higher numerical aperture enables patterning at substantially tighter pitches without resorting to the multi-patterning workarounds that the prior platform required at the most aggressive critical layers. In practical foundry terms, the High-NA platform reduces the number of exposure steps required for the topmost metal interconnect layers at the 2nm and sub-2nm nodes, which improves the cycle time, the wafer-start economics, and the yield envelope at those layers. The trade-off is that the higher numerical aperture optical envelope demands tighter mask blank, resist, and calibration specifications that the broader ecosystem is still maturing through 2026 and 2027.

Why is the High-NA contribution at TSMC's Fab 20 limited to the topmost metal layers rather than covering the broader critical-layer envelope?

The limitation to the topmost four-to-six metal layers is principally a stochastic-defect issue at the foundry-side resist chemistry. The High-NA optical envelope, at single exposure with current resist chemistry, produces stochastic patterning errors at a rate that the foundry-side mask and resist stack has not yet closed across the full critical-layer set. The path forward — through the JSR and Tokyo Ohka next-generation EUV-3 resist family scheduled for production qualification in late 2026 — extends the High-NA envelope to the broader critical-layer set through 2027. Fab 20 phase one is shipping with the constrained envelope because the resist qualification is not complete.

How much does an ASML High-NA system actually cost, including service and consumables?

The list price for an EXE:5200 is 380 million dollars, with delivery, installation, initial calibration, and first-year service pushing the total commitment at customer-side acceptance to approximately 425 million dollars. The five-year total cost of ownership — incorporating ongoing service, consumables, mask blank set, and the resist chemistry envelope — runs to approximately 510 million dollars per system. Volume customers like TSMC negotiate per-system pricing approximately 20 million below list through service-bundling and volume-rebate structures. Smaller customers face the list figure with limited room for negotiation.

What is Imec's role in the High-NA ecosystem, and why does the consortium have one of the four systems?

Imec is the European research consortium that anchors the broader EUV process development effort, running collaborative programmes with ASML, the four leading foundries, the equipment vendors, and the leading resist chemistry suppliers. The Imec installation at Leuven is the platform on which the next-generation resist chemistry and the broader process integration workstreams are co-developed alongside the foundry-side production environments. The consortium installation enables the precompetitive technical work that the broader ecosystem depends on, and it gives the European industrial AI ecosystem access to leading-edge process development that it cannot deliver through domestic fab construction on the current capex commitments.

Can Chinese foundries access High-NA EUV through any commercial pathway?

No. The Dutch government's export-control regulation, coordinated with the US Department of Commerce's Entity List framework, prohibits the export of the EXE:5200 to mainland Chinese customers and extends the prior-generation NXE:3800 prohibition that has been in force since late 2023. The regulatory posture has been characterised as a technology-tier control rather than a country-specific embargo, but the practical effect for Chinese foundries is identical: no commercial pathway exists for High-NA EUV procurement, and the structural durability of the regime has held through eighteen months of political and administrative transitions in both the Netherlands and the US.

When will Samsung Foundry's SF1.4 process node be competitive with TSMC's A14, and what would competitive parity look like?

The published roadmaps target risk production for both nodes in 2027 with volume production in 2028. Competitive parity would require Samsung Foundry to deliver SF1.4 at yield curves comparable to TSMC A14 at the same point in the process maturity cycle, and to secure design-in commitments from at least one of the major mobile or accelerator customers that have been on TSMC's side for prior node generations. The two prior generations — SF3 and SF2 — both missed their original timelines by approximately two quarters and underperformed TSMC's equivalent nodes on yield. The internal Samsung Foundry posture on SF1.4 has been characterised as more disciplined, but the competitive recovery is, on the published external indicators, not yet evidenced at the level that would support a confident parity forecast.