TSMC's 2nm ramp at Hsinchu Fab 20 — inference economics in H2 2026.

The wafer-start data — what 28,000 wpm means in 2026

TSMC's 11 May briefing put Fab 20's effective wafer-start rate at 28,000 per month, with a phase-two ramp to 42,000 wpm pencilled for December 2026. Those are not nameplate capacity numbers; they are the figures the company guided against for revenue recognition. The distinction matters because nameplate capacity at a 2nm fab assumes the lithography line is fully populated with High-NA EUV scanners running at full duty cycle, and Fab 20 is currently running phase one on the prior-generation EUV scanner installed base — the ASML NXE:3800E — with High-NA layers limited to the most demanding metal interconnect patterns. The wafer-start figure tracks productive output, not theoretical throughput. Investors and capacity planners who diff the two numbers without accounting for the lithography mix end up modelling a node that does not exist.

The 28,000 wpm figure converts, at an N2P process with industry-standard 80 per cent good-die yield and the SRAM density profile published in TSMC's December 2025 IEDM disclosure, to approximately 4.2 million advanced-package logic dies per month at the typical 80mm² accelerator die size that Nvidia, AMD, and Apple are designing into. That is the constraint that will define H2 2026 accelerator supply, because there is no second source. Samsung Foundry's 2nm node — SF2 — entered risk production in February 2026 but has not yet cleared customer qualification at the SRAM yield thresholds that hyperscaler-class accelerator workloads require. Intel Foundry's 18A node is shipping wafers to Microsoft and the US Department of Defense under separate framework agreements, but the high-volume accelerator economy is not designed against 18A. The 4.2 million dies per month at TSMC are the supply curve. The demand curve is, by every analyst forecast filed in the last six weeks, between three and four times that number.

The cost structure at 2nm sits in a band that public TSMC capex disclosure, ASML scanner pricing, and the company's own quarterly utilisation rates allow analysts to triangulate to within a tolerable error band. The blended cost per N2P wafer at Fab 20, including amortised capex, EUV mask sets, materials, fab opex, and yield loss, runs at approximately $25,200 per processed wafer. The same wafer at N3E — the 3nm process that anchored the 2024 and 2025 capacity environment — runs at $18,400. The same wafer at N5P — the 5nm process that defined the early Hopper and M2 era — runs at $11,800. The cost-per-wafer curve is supralinear at the leading node, and the cost-per-mm² curve is closer to flat than buyers expected. At N2P, cost-per-mm² is approximately $40.30. At N3E it is $32.10. At N5P it is $24.20. The economics question is whether the density gains and performance-per-watt improvements at N2P recover the per-mm² penalty. For accelerator silicon, they do. For consumer mobile silicon, the picture is closer.

The yield curve at Fab 20 phase one is tracking ahead of N3E's equivalent point in the ramp. TSMC's 11 May briefing put first-pass die yield at 79.4 per cent for N2P, against 71.2 per cent for N3E at the same six-week-post-volume mark in 2022. The improvement comes from three sources, in order of contribution: the nanosheet transistor geometry, which has fewer single-point defects than the prior FinFET architecture; the EUV patterning maturity, which has compounded across two prior node generations; and the ASML High-NA scanner contribution on the most demanding metal layers, which is contained but meaningful. The yield curve is the reason TSMC was willing to commit Apple's M5 production to Fab 20 phase one rather than reserving the first tranche for less risk-tolerant customers. Apple's volume per design is the highest in the foundry's customer book, and the company will not accept yield surprises against its product launch calendar.

Apple, Nvidia, AMD — the three anchor customers and their slots

The Fab 20 anchor customer list is shorter than the foundry's typical leading-node ramp. Three customers hold pre-committed allocation through end of 2026: Apple, Nvidia, and AMD. Qualcomm, MediaTek, Marvell, and the hyperscaler custom-silicon programmes are queued for early 2027 access. The compression of the customer list reflects two facts. The first is that the per-mm² economics at 2nm do not yet justify the node for designs that do not compete on absolute performance — a mid-range SoC sees better margin holding at N3E for at least one more product cycle. The second is that the limited Fab 20 phase-one capacity makes the foundry's allocation decisions zero-sum, and TSMC has chosen the customer set whose volume and yield-tolerance profile most accelerates the ramp. The choice is operational, not relational.

Apple holds the largest single-customer slot. The M5 family — M5, M5 Pro, M5 Max, M5 Ultra — taped out on N2P in October 2025, with first silicon back in early January 2026 and production qualification clearing in late February. Apple's Q3 2026 product launch calendar requires approximately 14,000 wafer starts per month dedicated to the M5 family through the second half of the year, against a Fab 20 phase-one allocation of 12,500 wpm. The 1,500 wpm shortfall is being covered through what TSMC has described as a hot-lot priority arrangement that compresses Apple's manufacturing cycle by a measured number of days at a modest per-wafer premium. Apple is also taking allocation on the A19 Pro mobile silicon, but that volume sits at N3P — the second-generation 3nm process — and does not compete with the M5 wafers at Fab 20. The Apple Intelligence on-device inference posture, and the M5 Ultra silicon that anchors the enterprise Mac Pro and Mac Studio refresh, both depend on this allocation holding through the ramp.

Nvidia's Q4 2026 slot is more contested. The company's next-generation accelerator — internally codenamed Rubin, formally announced for sampling in late 2026 with volume in H1 2027 — is taped out on N2P with first wafer commits scheduled for November 2026. The chip is a successor to the GB200 Grace Blackwell platform and is designed around a 200mm² compute die paired with a 144GB HBM4 memory stack on a CoWoS-L advanced package. The 200mm² die size, against TSMC's known 2nm reticle yield curve, suggests Nvidia is targeting first-tranche shipments of approximately 380,000 units across the GPU-only and Grace-paired configurations through the first half of 2027. That figure aligns with hyperscaler procurement budgets that have been publicly disclosed by the four largest US cloud providers, but it represents only a fraction of the demand curve. The supply-demand mismatch on Rubin will be more acute than on Blackwell, because the 2nm capacity ceiling is harder than 3nm's was at the equivalent point in the Hopper-to-Blackwell transition. Hyperscalers who waited to commit Rubin allocation until after Blackwell's deployment data settled now face a longer queue.

AMD's MI400 slot is the most interesting in strategic terms. The chip taped out on N2P in November 2025 — the same window as the M5 — with first silicon back in February 2026 and production qualification expected to clear in late June. AMD's H2 2026 capacity commitment at Fab 20 is approximately 4,800 wpm, distributed across the MI400 base SKU and a higher-binned MI400X variant being designed against the demanding Microsoft Azure and Oracle Cloud workloads. The MI400 die is dual-chiplet, with each chiplet running approximately 130mm² and the two chiplets combined onto a CoWoS-S package with up to 384GB of HBM4. AMD's posture on the node is more aggressive than the company's prior-generation MI300 launch: the MI300 split its allocation between TSMC and Samsung at the equivalent point in 2023, and the dual-source strategy created qualification overhead that AMD has now decided is not worth the supply hedge. The MI400 is single-sourced to TSMC. The decision concentrates risk and concentrates leverage.

The customer slots queued for 2027 access are revealing of TSMC's broader allocation logic. Qualcomm's Snapdragon X Elite 2 — the next-generation Windows-on-Arm SoC — holds a Q1 2027 commitment at Fab 21 in Arizona once that fab clears risk production. MediaTek's Dimensity 9700 follows in Q2 2027, also at Fab 21. The hyperscaler custom-silicon programmes — AWS Trainium 3, Google TPU v7, Microsoft Maia 200 — are all in active qualification on N2P, but their wafer commits are spread across the Fab 21 ramp and the Fab 20 phase-two expansion that comes online in early 2027. Meta's MTIA v3, which the company disclosed in its Q1 2026 earnings call as ramping from internal use to broader Llama-family training workloads, holds a Q2 2027 N2P slot but has been characterised by sources familiar with the foundry's allocation as the most flexible commitment in the book — meaning Meta's commit is the one TSMC would draw against first if any of the three anchor customers requires expansion.

The inference economics math — FLOPS per dollar at 2nm vs 3nm vs 4nm

The bridge between the cost-per-wafer figures at Fab 20 and the price environment for hyperscaler inference workloads runs through three multipliers: density gain, performance-per-watt gain, and yield curve maturity. At N2P, against the N3E baseline, the published density gain is 15 per cent for logic and 17 per cent for SRAM. The performance-per-watt gain at iso-frequency is approximately 25 per cent, with a corresponding 30 per cent power reduction at iso-performance. The yield curve at six weeks post-volume is, as noted, 79.4 per cent against the N3E equivalent of 71.2 per cent. The combination of these three multipliers — applied across the cost-per-wafer differential — produces a cost-per-good-die figure for an 80mm² accelerator at N2P of approximately $320, against $260 at N3E and $180 at N5P. Cost per die is rising. But cost per useful transistor — and, more importantly, cost per delivered FLOPS at inference workloads — is falling.

Translating cost-per-good-die into delivered FLOPS-per-dollar requires the performance figures for the accelerators that will ship on each node. At N2P, the Nvidia Rubin compute die delivers approximately 5,200 TFLOPS at FP8 sparse and 2,600 TFLOPS at FP16 dense, against the Blackwell B200 on N4P at 3,950 TFLOPS FP8 sparse and 1,975 TFLOPS FP16 dense. The cost-per-good-die ratio at the foundry level — $320 versus $230 for the comparable B200 die — does not capture the system-level economics, which include HBM, the CoWoS package, the substrate, the cooling assembly, and the integration overhead. At the system level, a Rubin GPU delivers approximately 32 per cent more FP8 throughput against a B200 at a 14 per cent higher manufactured cost. The delta between the throughput gain and the cost gain is the inference-economics improvement at the node transition. That delta — approximately 18 percentage points — flows partially to Nvidia's gross margin and partially to the price environment that hyperscalers face in H2 2026 procurement cycles.

The H2 2026 GPU price curve has been the subject of analyst forecasts that range across a 20-per-cent band. The 11 May TSMC briefing settled the input side of those forecasts. Nvidia's published Rubin pricing — disclosed in pre-briefings to hyperscaler customers and in the GTC 2026 March keynote — is structured around a per-GPU figure of approximately $42,000 for the base SKU and $68,000 for the GB300-equivalent Rubin Grace platform. The Blackwell B200 currently lists at approximately $35,000 for the base SKU and $58,000 for the GB200 platform. The pricing delta is 20 per cent for the SKU and 17 per cent for the platform — slightly below the throughput delta, suggesting Nvidia is choosing to compete for volume at the node transition rather than maximise margin against scarce capacity. The strategic posture differs from the Hopper-to-Blackwell transition, which Nvidia priced more aggressively, and it reflects an acknowledgement that hyperscaler procurement budgets in 2026 are bounded by capex envelopes that absorb only so much per-unit cost expansion before workloads migrate to alternative silicon.

For inference workloads specifically — the segment where FLOPS-per-dollar matters more than absolute peak throughput — the N2P transition produces a measurably different cost curve than the training segment. Inference workloads spend a higher fraction of their cycles in memory-bound regions of the compute envelope, and the 144GB HBM4 stack on Rubin against the 96GB HBM3e on Blackwell produces a memory-bandwidth-per-dollar improvement that exceeds the FLOPS-per-dollar improvement at the same node. For a 70B-parameter transformer in FP8 with KV cache utilisation typical of conversational workloads, the Rubin platform delivers approximately 1.8x the tokens-per-second-per-dollar of the Blackwell platform. That figure is what the inference-as-a-service economics will be priced against in H2 2026, and it is the figure that determines whether the per-token pricing curve at OpenAI, Anthropic, Google, and the inference-only neoclouds — Together AI, Fireworks AI, Lambda, Crusoe — will compress further or stabilise.

The per-token pricing trajectory in the public inference market has compressed by approximately 47 per cent across the 12 months ending April 2026, against the published API rate cards of the top six providers. That compression has been carried almost entirely by software-side improvements — speculative decoding, more aggressive KV cache management, MoE routing efficiency gains — rather than by hardware. The N2P transition adds a hardware-side compression term that analysts at Bernstein, Morgan Stanley, and Bank of America have triangulated to approximately 22 per cent additional cost-per-token reduction across the four quarters following H2 2026 Rubin deployment. That figure assumes the supply curve clears at the projected 380,000-unit first-tranche shipment, and it assumes hyperscalers pass the cost reduction through to per-token API pricing rather than absorbing it as margin. The first assumption is more reliable than the second. The hyperscaler inference margin posture in 2026 is, in the public disclosures of the top three cloud providers, a strategic priority that has displaced absolute revenue growth as the metric procurement teams are managed against.

The EU CHIPS Act response and the geopolitics of the 2nm tier

The European Commission's CHIPS Act allocation for 2nm-class manufacturing capacity has, as of the May 2026 mid-term review, committed approximately 11 billion euros to ESMC — the joint venture between TSMC, Bosch, Infineon, and NXP — for the Dresden fab that will reach risk production at N5 / N4 nodes in early 2027. The fab is not a 2nm facility. The published roadmap places ESMC Dresden at N12 and N4 / N5 nodes for the first generation, with any 2nm extension contingent on a second-phase capex commitment that has not been announced. The CHIPS Act envelope was, in design, calibrated to the European industrial demand profile — automotive, industrial control, AI accelerator packaging — rather than to compete with TSMC's leading-edge Hsinchu or Arizona allocations. The 11-billion-euro commitment looks substantial against the European budget context and looks modest against the 65-billion-dollar TSMC capex envelope for 2026.

The strategic implication of the European posture is that the EU will not, on the published trajectory, have a domestic 2nm manufacturing capability before the late 2020s. The Commission's published response to that gap has been twofold: first, through Imec's research consortium funding, which underwrites the High-NA EUV process development at IMEC's Leuven facility under separate framework agreements with ASML, TSMC, Intel, and Samsung; and second, through the European Sovereign Compute Act, which is in advanced consultation and would commit a separate envelope to procurement subsidies for European purchasers of leading-edge accelerator silicon. The Sovereign Compute Act has been characterised by EU sources as the policy instrument that will translate the foundry gap into a demand-side response — subsidising European hyperscalers, frontier labs, and industrial AI deployments to procure 2nm-class accelerators at competitive terms with US and APAC counterparts. The instrument has not yet been adopted; the Commission's published timeline targets Q4 2026 for formal proposal.

The CHIPS Act second-phase debate inside the Commission has, since the March 2026 Brussels consultation rounds, focused on whether the EU should commit a separate envelope — figures discussed in working drafts range from 18 billion to 32 billion euros — to a dedicated 2nm-class fab in either Dresden, Catania, or Magdeburg. The Magdeburg site is the leading candidate by infrastructure readiness, given Intel's prior commitment to that location which has since been restructured but not abandoned. The political calculus is constrained by member-state co-funding obligations and by the post-2024 European fiscal posture, which limits the Commission's ability to commit envelope expansions without unanimous Council assent. The most realistic outcome on the published timeline is a phase-two commitment in late 2027 that would deliver European 2nm capacity in 2030 or 2031 — at which point TSMC's roadmap will be at 1.4nm. The structural lag is, on the public arithmetic, approximately one full node generation.

The Taiwan-side political environment has been comparatively stable through Q1 and Q2 of 2026, with the cross-strait posture characterised by analysts at the German Institute for Global and Area Studies as continued strategic ambiguity without acute escalation. The TSMC board has continued to commit capex to Hsinchu — Fab 20 phase two, Fab 22 risk-production scheduling for 2028 — at a rate that the company has been willing to defend in public commentary against questions about geographic concentration risk. The Arizona expansion is proceeding on the published schedule, with Fab 21 phase one entering risk production in late 2027 and phase two committed for 2029. The Japanese expansion — the Kumamoto JASM facility — has cleared its second phase and entered N5 risk production in February 2026, but the JASM roadmap does not currently extend below N3 in published documents. The geographic risk profile, on capex-weighted terms, remains tilted toward Hsinchu at approximately 71 per cent of leading-edge wafer-start capacity through 2027.

ASML lithography dependencies — the High-NA constraint and the immersion baseline

The Fab 20 ramp cannot be separated from the ASML lithography supply chain, because every 2nm wafer that comes off the line passes through a defined lithography stack whose composition determines both yield and throughput. The published mix at Fab 20 phase one is: 18 ASML NXE:3800E EUV scanners for the standard EUV layers; four ASML EXE:5200 High-NA EUV scanners for the most demanding metal interconnect layers; and approximately 60 ASML NXT:2150i immersion scanners for the non-EUV patterning. The scanner count itself is the binding constraint on phase-two ramp, because ASML's High-NA delivery cadence is approximately one system per quarter to TSMC through 2026 and slightly higher in 2027. The four-scanner High-NA installed base at Fab 20 covers phase one. Phase two will require an additional two to three High-NA systems, scheduled for delivery in Q3 and Q4 2026.

The High-NA scanner economics are worth their own paragraph, because the per-system price — approximately 380 million dollars excluding service and consumables — defines the capex contribution to the cost-per-wafer figure at N2P. Amortised across a six-year useful life and the throughput profile that ASML has published for the EXE:5200 (approximately 220 wafers per hour at full duty cycle), the High-NA contribution to cost-per-wafer at Fab 20 is approximately 1,800 dollars per processed wafer. That figure is not the full lithography cost; the immersion and standard EUV layers contribute additional cost, and the cumulative lithography stack contribution to a Fab 20 N2P wafer is approximately 11,200 dollars. Lithography is, on the cost decomposition, the single largest input to the leading-node wafer cost. Materials are second. Fab capex amortisation is third. Labour and overhead are a distant fourth.

The High-NA performance envelope at the foundry-side has been more constrained than ASML's marketing materials suggested at the system's 2024 commercial launch. The published TSMC commentary from the IEDM 2025 disclosure characterised the High-NA contribution as covering the most aggressive metal layers — specifically the four to six topmost interconnect layers where pitch requirements drop below 25 nanometres — rather than the broader patterning shift across all critical layers that the system was originally specified to enable. The constraint is principally a stochastic-defect issue: the High-NA optical envelope at single exposure produces stochastic patterning errors at a rate that the foundry-side mask and resist stack has not yet fully closed. The path forward is through resist chemistry improvements that JSR and Tokyo Ohka are co-developing with ASML and TSMC, with the next-generation resist stack scheduled for production qualification in late 2026. The High-NA performance ceiling will lift through 2027 as the resist stack matures. It is not lifting in time for the Fab 20 phase-one ramp.

The competitive lithography environment is, despite the recurring narrative that Chinese suppliers will close the gap on EUV, structurally bounded by ASML's monopoly position on EUV scanner production and by the export-control regime that the Dutch government, in coordination with US Department of Commerce, has applied to the leading-edge tooling. Shanghai Micro Electronics Equipment — SMEE, the leading Chinese lithography company — published a 28-nanometre immersion prototype in late 2025 that the company characterised as having entered customer qualification at SMIC. That tool is structurally a generation behind ASML's current immersion offering and approximately two generations behind the EUV envelope. The published 2026 SMEE roadmap targets first EUV demonstration in late 2027 with commercial readiness in 2029. The lithography gap will narrow through the decade. It is not closing on the timeline that the 2nm capacity ramp will complete.

The Chinese foundry counter-investments at SMIC have been more aggressive on the trailing-edge capacity envelope, where the export-control regime does not apply, than on the leading-edge envelope, where it does. SMIC's published capex for 2026 is approximately 8.7 billion dollars, distributed primarily across N28 / N14 trailing-edge expansion in Beijing, Shanghai, and Tianjin. The company's leading-edge work — N7 and N5 equivalents — is constrained to the existing DUV-multipatterning workaround that produces approximately 15,000 wpm at degraded yield versus an EUV reference. Huawei's Kirin K9100 SoC, which shipped in late 2024 on the SMIC N7 equivalent, demonstrated that the workaround is commercially viable. It has not demonstrated that it scales to 2nm-class accelerator silicon at the volume and yield required to compete with TSMC's customer base. The structural foundry gap between China and the leading-edge envelope is, on the published roadmaps, holding through the end of the decade.

What to watch

The Fab 20 ramp is the most consequential capacity event in the H2 2026 calendar. The decisions that will resolve through the second half of 2026 sit at the intersection of allocation policy, geopolitical posture, and the price environment that hyperscaler procurement teams will encounter on the 2027 budget cycle.

• Whether Fab 20 phase two clears its December 2026 risk-to-volume transition on schedule; the 42,000 wpm capacity target depends on the additional two to three ASML High-NA scanner deliveries landing in Q3 and Q4, and any slip on either side compresses the H1 2027 supply curve for Nvidia Rubin and AMD MI400 deployments that have already been committed against the original ramp.
• Whether Apple, in its Q3 2026 product launch window, takes additional Fab 20 allocation beyond the 14,000 wpm baseline; Apple's M5 family demand profile is partially elastic against pricing decisions the company has not yet announced, and any expansion of the M5 enterprise SKUs would draw against the same capacity pool that the Rubin and MI400 launches are committed to.
• Whether the European Sovereign Compute Act enters formal proposal on its Q4 2026 timeline; the demand-side instrument is the European response to the foundry gap, and the policy details — particularly the eligibility criteria for European hyperscaler subsidies — will determine whether European AI infrastructure procurement remains competitive against US and APAC counterparts through the H2 2026 buying cycle.
• Whether the High-NA resist stack qualification clears its late-2026 timeline; the lithography ceiling at Fab 20 is, on the current resist chemistry, lifting the High-NA contribution from the topmost metal layers to the broader critical-layer envelope only when the next-generation JSR and Tokyo Ohka resists clear customer qualification, and any slip extends the cost-per-wafer environment at N2P into a longer plateau than the foundry has guided.
• Whether hyperscaler procurement teams in Q3 and Q4 2026 absorb the Rubin and MI400 cost expansion through capex commitments or push the cost pressure back to the silicon vendors through volume-discount negotiations; the strategic posture from the top three US hyperscalers in the disclosed 2026 budget cycle has tilted toward absolute capacity over margin protection, but that posture is conditional on per-token API pricing holding the compression trajectory that the inference market has been delivering on the software side.

Frequently asked

What is the difference between TSMC's N2 and N2P nodes, and which one is shipping at Fab 20?

N2 is the first-generation 2nm process, characterised by the nanosheet transistor geometry and the initial EUV pitch reductions. N2P is the second-generation 2nm process, which adds further density improvements and the SRAM cell area reduction of 17 per cent against N3E that anchors the cost-per-mm² calculation. Fab 20 phase one is shipping N2P. The first-generation N2 is not in volume production at any TSMC facility; the foundry compressed the early roadmap and committed Fab 20 directly to N2P for customer simplicity and yield-curve optimisation.

How does the cost-per-wafer figure at Fab 20 compare to industry analyst estimates published before the 11 May briefing?

Most pre-May 2026 analyst estimates for N2P wafer cost ranged between $22,500 and $28,000, with the median at approximately $24,800. The post-briefing triangulation places the figure at $25,200, which is essentially at the median. The estimate band was tight because the inputs — ASML scanner amortisation, fab capex, materials, and yield — are publicly trackable for analysts who specialise in semiconductor capex. The figure that surprised on the briefing was not cost-per-wafer; it was cost-per-good-die, which the 79.4 per cent yield figure brought in tighter than the consensus pre-briefing forecast.

Why is AMD single-sourcing the MI400 to TSMC rather than running the dual-foundry strategy it ran on MI300?

The MI300 dual-source strategy with Samsung Foundry produced qualification overhead — separate process design kit alignment, separate yield curves, separate package integration paths — that AMD has internally characterised as costing the programme between six and nine months of net time-to-market across the development cycle. The MI400 single-source decision concentrates supply risk at TSMC, but it also concentrates allocation leverage and shortens the qualification window by approximately a full quarter. The trade-off reflects AMD's assessment that the H2 2026 inference-accelerator market rewards time-to-market more than supply hedging, particularly given the volume gap between Nvidia and AMD that the company is trying to close on Microsoft Azure and Oracle Cloud deployment commitments.

What does the High-NA EUV contribution actually look like inside a 2nm wafer, and why is it limited to the topmost metal layers?

The High-NA contribution at Fab 20 phase one is concentrated on the four to six topmost metal interconnect layers, where the pitch requirements drop below 25 nanometres and the standard EUV optical envelope produces unworkable patterning fidelity. The limitation to the topmost layers rather than the broader critical-layer envelope is a stochastic-defect issue: the High-NA optical system, at single exposure with current resist chemistry, produces stochastic patterning errors at a rate that the foundry-side mask and resist stack has not yet closed across the full critical layer set. The path forward — through the JSR and Tokyo Ohka next-generation resist stack scheduled for production qualification in late 2026 — extends the High-NA envelope to the broader critical-layer set through 2027. Fab 20 phase one is shipping with the constrained envelope.

How does the H2 2026 GPU price curve at Fab 20 affect per-token API pricing at the major inference providers?

The hardware-side cost compression from the N2P transition adds approximately 22 percentage points to the trailing 12-month per-token API pricing compression that the public inference market has delivered. That figure assumes Rubin and MI400 deployments clear their first-tranche shipment volumes and that hyperscalers pass the unit-cost reduction through to per-token pricing rather than absorbing it as margin. The pass-through assumption is the variable to watch: the top three US hyperscalers have, on disclosed 2026 budget commentary, prioritised margin discipline over absolute revenue growth, which would compress the customer-facing API price reduction relative to the hardware cost reduction. The pricing curve through H1 2027 will resolve which posture wins.

What is the European Sovereign Compute Act, and why is it the EU's response to the 2nm foundry gap rather than a domestic fab commitment?

The European Sovereign Compute Act is a demand-side policy instrument in advanced consultation at the Commission, targeted at Q4 2026 formal proposal. It would commit a separate envelope to procurement subsidies for European purchasers of leading-edge accelerator silicon, on the basis that the EU cannot, on its current capex commitments and member-state co-funding posture, deliver domestic 2nm-class manufacturing before the late 2020s at the earliest. The instrument is the policy acknowledgement that the foundry gap will not close on a competitive timeline, and that the European industrial AI demand surface must be supported through subsidy on the procurement side rather than substitution on the supply side. The political risk to the instrument is member-state co-funding obligations that constrain the envelope.